product # : uw2453 confidential doc. #: ds-2453-01 page 1/ 24 revised date: march 18, 2005 uw2453/2453l data sheet (preliminary) doc. #: ds-2453-01 the content of this technical information is subject to change without notice. please contact ubec for further information. all rights strictly reserved. any portion of this paper shall not be reproduced, copied, or transformed to any other forms without permission from uniband electronics corp. . uniband electronics corp. (taiwan) uniband electronics corp. (u.s.a.) 3f-2, no. 192, dongg uang rd. 826, north hillview drive, milpitas. hsinchu 300, taiwan ca 95035, usa tel: +886-3-5729898 tel: +1-408-935-7888 fax: +886-3-5718599 fax: +1-408-935-7889 http:// www.ubec.com.tw
product # : uw2453 confidential doc. #: ds-2453-01 page 2/ 24 revision history revision date description of change 0.0 march 18, 2005 initial version
product # : uw2453 confidential doc. #: ds-2453-01 page 3/ 24 1 product description the uw2453 is a fully integrated single-chip transceiver (including pa) specifically designed for ieee802.11b/g wireless local area networks (wlans) applications. it supports data rate 6, 9, 12, 18, 24, 36, 48 and 54 mbits/s in ofdm mode, 5.5 and 11 mbits/s in cck mode, 1 and 2 mbits/s in dsss mode. the uw2453 integrates a receiver, transmitter, vco and pll as well a power amplifier into a single ic. it uses direct conversion radio architecture to minimize external parts count and power consumption. only one or two switches, one rf bandpass filter, one lowpass filter and several passive components are required to build a spec compliant 11b/g radio. the patented dc cancellation technique allows the receiver set its gain at super fast speed as required for the gain settling in the ofdm mode. the patent pending power amplifier design assures a very good tx linearity at a minimum current consumption. the uw2453 is fabricated by advanced sige bicmos process and is housed in a 48-pin qfn 7x7 mm 2 package. the UW2453L is a lower output power and lower current (tx) version of the uw2453. the UW2453L has the same package and pinout. the low power consumption of the uw2453/UW2453L makes it an ideal candidate for wlan applications in desktop/laptop pc, handheld devices and mobile handsets. 2 features o ieee 802.11 b/g specification compliant o 6, 9, 12, 18, 24, 36, 48 and 54 mbit/s in ofdm mode o 1, 2, 5.5 and 11 mbits/s in dsss and cck mode o 2.4 to 2.5 ghz frequency operation o ?87 dbm sensitivity at 11 mbits/s cck mode o ?73 dbm sensitivity at 54m bits/s ofdm mode o high performance and low power consumption o zero if receive and direct conversion transmit architecture o integrated low phase noise vco and pll loop filter o integrated power amplifier o shared rx and tx filter structure to minimize die size o high performance ? frequency synthesizer o high receiver and rssi dynamic range o support antenna diversity o patented super fast dc cancellation o ultra fast digital rx and tx gain settling time o complementary 3-wire bus rx and tx gain control o +18 dbm transmit power (54 mbits/s ofdm) for uw2453 o +14 dbm transmit power (54 mbits/s ofdm) for UW2453L o +21 dbm transmit power (11 mbits/s cck) for uw2453 o +17 dbm transmit power (11 mbits/s cck) for UW2453L o mimo transceiver support o 5 ua sleep mode o support 2.7 ~ 3.6 v supply o small 48-pin leadless qfn 7x7 mm 2 package o sige bicmos technology o low external component count
product # : uw2453 confidential doc. #: ds-2453-01 page 4/ 24 3 block diagram and pin configuration figure 1. uw2453/UW2453L block diagram and pinning
product # : uw2453 confidential doc. #: ds-2453-01 page 5/ 24 table 1. pin descriptions pin type abbreviation: a = analog, d = digital, i = input, o = output pin symbol type description 1 vdd_pa1 pa power supply. bypass with a cap as close to the pin as possible. 2 gnd_pa pa ground 3 pa_out1 ao pa 1 st stage open collector output. 4 pa_out2 ao pa 2 nd stage open collector output. it is tx rf output. 5 vdd_pa2 pa power supply. bypass with a cap as close to the pin as possible. 6 pa_det pa power detector output. 7 vdd_lna lna power supply. bypass with a cap as close to the pin as possible. 8 rfin_p ai lna differential rf input (+) 9 rfin_m ai lna differential rf input (-) 10 vdd_mxr rx mixer power supply. bypass with a cap as close to the pin as possible. 11 rxtx di rx and tx mode select 12 paon di pa turn on/off control 13 vco_tune pll loop cap to ground 14 gnd_vco vco ground 15 vreg_out regulated supply for vco. bypass with caps to ground 16 vdd_lo lo power supply. bypass with a cap as close to the pin as possible. 17 vdd_pll pll power supply. bypass with a cap as close to the pin as possible. 18 vdd_cp charge-pump supply. bypass with a cap as close to the pin as possible. 19 gnd_cp ground for charge pump circuit 20 lock/gs dio synthesizer lock indicator or gs1~7 latch control 21 data di three-wire bus data signal 22 en di three-wire bus enable 23 vdd_buf clock buffer supply. bypass with a cap as close to the pin as possible. 24 ref_clk ai reference clock input 25 gnd_dig ground for digital circuit 26 vdd_dig digital circuit supply. bypass with a cap as close to the pin as possible. 27 clk di three-wire bus clock 28 tx_ip ai transmitter i channel differential input (+) 29 tx_im ai transmitter i channel differential input (-) 30 tx_qp ai transmitter q channel differential input (+) 31 tx_qm ai transmitter q channel differential input (-)
product # : uw2453 confidential doc. #: ds-2453-01 page 6/ 24 32 vdd_b analog circuit supply. bypass with a cap as close to the pin as possible. 33 rx_qm ao receiver q channel differential output (-) 34 rx_qp ao receiver q channel differential output (+) 35 rx_im ao receiver i channel differential output (-) 36 rx_ip ao receiver i channel differential output (+) 37 rssi ao rssi output 38 rbias bias resistor pin. connect an 12 k (1%) resistor to the bias ground. 39 gs7 di 2 db vga gain control pin 40 gs6 di 4 db vga gain control pin 41 gs5 di 8 db vga gain control pin 42 gs4 di 16 db vga gain control pin 43 gs3 di 32 db vga gain control pin 44 gs2 di lna/filter gain control pin 45 gs1 di lna/filter gain control pin 46 vdd_mxr rx mixer power supply. bypass with a cap as close to the pin as possible. 47 vdd_vga rx vga power supply. bypass with a cap as close to the pin as possible. 48 pa_drv ao pa driver stage open collector output gnd_slug chip ground. connect to pcb ground plane using several via.
product # : uw2453 confidential doc. #: ds-2453-01 page 7/ 24 4 operation condition table 2. absolute maximum ratings parameter min max unit storage temperature -55 +150 c supply voltage vdd pin to ground -0.5 +4.2 v voltage applied to input pins -0.5 vdd+0.5 v voltage applied to output pins -0.5 vdd+0.5 v short circuit duration, to gnd or vdd 5 sec table 3. recommended operating conditions parameter min typ max units ambient operating temperature -30 +85 c supply voltage 2.7 3.0 3.6 v logical high input voltage (for di type pins) vdd-0.4 vdd+0.3 v logical low input voltage (for di type pins) -0.3 0.4 v 5 current consumptions table 4. current consumptions t a = 25 o c, vdd = 2.85 v chip mode condition min typ max unit sleep register 0000, mode bits = 0000 5 ua idle register 0000, mode bits = 0001 28 ma tx (18 dbm ofdm uw2453) register 0000, mode bits = 0010, rxtx=0 228 ma tx (14 dbm ofdm UW2453L) register 0000, mode bits = 0010, rxtx=0 164 ma rx register 0000, mode bits = 0010, rxtx=1 76 ma cal_fil register 0000, mode bits = 0011 3 ma cal_vco register 0000, mode bits = 0100 22 ma reset register 0000, mode bits = 0111 na ma
product # : uw2453 confidential doc. #: ds-2453-01 page 8/ 24 6 uw2453/UW2453L functional description the uw2453/UW2453L receiver consists of a lna, a pair of down-conversion mixers, i&q channel filters, i&q variable gain amplifiers (vga), rssi and programmable dc blocking cancellation blocks. the lo generation circuits (vco, pll and buffers) are shared with the receiver and transmitter. the lna features a differential input for high performance. an external balum matching network is required. the lna has 2 stepped gains. along with one stepped gain inside the channel filter, three stepped gains are achieved in the receive chain from the lna to the channel filters and they are controlled by two digital i/o pins, gs1 and gs2. the additional receive gain is realized by the rx vga. the rx vga has a gain resolution of 2 db and the gain is set by pins gs3~gs7. pin gs7 sets a two db change. since the rx gain is set by the digital i/o pins, fast gain settling is realized. the rx gain can also be set by the regular or 3-wire bus in addition to the pins gs1~gs7. the uw2453/UW2453L features a patented dc blocking circuit and the dc blocking circuit settles the receive dc offset for less than 10 mv at the rx outputs within 400 ns for any gain size change. to have a better control over the dc settling process, the settling time is programmable. to set a proper rx gain without a prior knowledge of the received signal strength, the uw2453/UW2453L only needs a maximum of three times of gain adjustment with the help of the high dynamic range rssi output. when the input signal is below ?41 dbm, only two times of gain adjustment is required thanks to the high dynamic range of the rssi circuit. the uw2453/UW2453L also supports antenna diversity. however, antenna diversity requires a total settling time equivalent to a maximum of four times of gain adjustment. that means if in no diversity case, the worst total gain settling time is 2.4 us, it is 3.2 us with diversity. before the receiver properly demodulates the signal, filter and vco calibration are needed. the filter and vco calibration finds the correct filter corner frequency and vco subband respectively, amid process, supply and temperature variation. the vco and filter calibration are self-contained and no support from dsp side is required. one unique feature is the receiver and transmitter share a pair of i&q channel filter in order to minimize the die size and cost. however, the filter bandwidth in rx and tx mode can be independently programmed, thanks to the innovative design. the switch between receive and transmit is controlled by pin rxtx in the rxtx_en chip mode. this pin also determines the filter bandwidth in conjunction with other register settings. the transmitter features direct conversion architecture with +18 dbm output power with ofdm signal and +21 dbm output power with cck signal with the integrated power amplifier for the uw2453 while the corresponding numbers are 14 and 17 dbm for the UW2453L. the output power adjustment range is 16 db in one db step. pins gs1 to gs4 are used to set the tx front end gain (16 db range). like the receiver, the tx front end gain can also be programmed by the regular 3-wire bus. the lo generation scheme of the uw2453/UW2453L employs a divided by 2 scheme to minimize pulling effect and to get a better phase imbalance. the vco operates at the twice of the channel frequency. additional feature is the ? frequency synthesizer having a fine frequency resolution. the wider loop bandwidth allowed by the ? frequency synthesizer is also helpful in tracking the vco pulling and pushing effect. the vco has a switched band design such that low phase noise, low vco gain factor and high stability are realized. the advanced vco calibration scheme makes it possible that the carrier frequency is always in the middle of one of the vco bands. after reprogramming the channel frequency, a vco calibration action is required. the pll charge pump current is programmable so that the vco gain variation for different bands can be compensated. the uw2453/UW2453L has a power-up reset to set the registers to their default values. there is also a reset mode to allow the 3-wire bus to reset the ic at any time. after a reset, the uw2453/UW2453L automatically enters the sleep mode. pin 20 (lock/gs) is a special input/output pin. it can be programmed as the pll lock detector output or as an enable pin for pin gs1~gs7. if pin 20 is configured as the gs1~gs7 enable pin, when pin 20=1, any change on gs1~gs7 will cause rx or tx gain change. when pin 20=0, any change on gs1~gs7 has no effect
product # : uw2453 confidential doc. #: ds-2453-01 page 9/ 24 on rx/tx gain and the receiver or transmitter uses the last gs1~gs7 values when pin 20=1. that is a high to low transition will latch the gs1~gs7 value. this feature is useful so that multiple of the uw2453/UW2453L is used in a mimo configuration without doubling or tripling the parallel control pins.
product # : uw2453 confidential doc. #: ds-2453-01 page 10/ 24 7 receiver ac characteristics table 5. receiver ac characteristics typical values are at t a = 25 o c, vdd = 2.85 v, lo frequency=2.447 ghz parameter condition min typ max unit rf input frequency 2.4 2.5 ghz measured at balun matching input (dsss/cck) -97 10 rf input range measured at balun matching input (ofdm) -92 4 dbm lo frequency vco frequency divided by 2 2.4 2.5 ghz lo leakage measured at balun matching network input -65 dbm input return loss external matched to 50 source by a balun matching network and for all gain range -10 -12 db gs1=1, gs2=1 48 gs1=1, gs2=0 32 rx stepped voltage gain gs1=0, gs2=1 or 0 9 db rx vga maximum gain gs3 gs4 gs5 gs6 gs7 = 11111 46 db rx vga minimum gain gs3 gs4 gs5 gs6 gs7 = 00000 -16 db gs3 32 gs4 16 gs5 8 gs6 4 rx vga gain step gs7 (note 1) 2 db maximum rx voltage gain (note 2) gs1 gs2 gs3 gs4 gs5 gs6 gs7 = 1111111 94 db minimum rx voltage gain (note 2) gs1 gs2 gs3 gs4 gs5 gs6 gs7 = 0000000 -7 db gain settling time (note 3) any gain size change 300 ns gs1=1, gs2=1, vga gain = 22 db 3 gs1=1, gs2= 0, vga gain = 22 db 7 gs1=0, gs2=1, vga gain = 22 db 24 dsb noise figure (including matching) gs1=0, gs2=0, vga gain = 22 db 40 db gs1=1, gs2=1, vga gain = 16 db -12 gs1=1, gs2= 0, vga gain = 16 db -8 input ip3 (including matching) (note 4) gs1=0, gs2=1, vga gain = 16 db 10 dbm
product # : uw2453 confidential doc. #: ds-2453-01 page 11/ 24 gs1=0, gs2=0, vga gain = 16 db 21 gs1=1, gs2=1, vga gain = 16 db 30 gs1=1, gs2= 0, vga gain = 16 db 30 gs1=0, gs2=1, vga gain = 16 db 50 input ip2 (including matching) (note 5) gs1=0, gs2=0, vga gain = 16 db 66 dbm i&q gain mismatch without calibration -0.3 0.3 db i&q phase imbalance without calibration -2 2 deg passband ripple (peak-to-peak 0.3~8.5 mhz ) 0.5 db max group delay (peak-to-peak 0.3~8.5 mhz ) 50 ns attenuation @ freq >= 12 mhz 8 db attenuation @ freq >= 15 mhz 25 db channel filter characteristics (after calibration) attenuation @ freq >= 25 mhz 60 db cck adjacent channel attenuation @25 mhz referenced to in-band cck signal power 50 db ofdm adjacent channel attenuation @25 mhz referenced to in-band ofdm signal power 45 db 3 db dc blocking frequency after dc settling 10 khz input power ?95 ~ -40 dbm. gs1gs2=11 0.7 2 v input power ?90 ~ -22 dbm. gs1gs2=10 0.4 2 v linear rssi voltage output input power ?67 ~ 1 dbm. gs1gs2=01 or 00 0.4 2 v rssi slope average rssi voltage change per 1 db input level change 23.5 mv /db rssi error with ofdm short preamble -3 3 db rssi settling time gs1gs2=11 change to gs1gs2=10 or 0x while gs3=gs4=gs5=gs6=gs7=1 300 ns resistive rssi output load 10 k capacitive rssi output load 5 pf tx to rx switching time output signal within 1 db of final value with cw input 2 us resistive i&q output load pin to ground/differential 5/10 k capacitive i&q output load pin to ground/differential 6/3 pf nominal i&q output level with gain adjustment. differential peak to peak. 1000 mv pp output 1 db compression differential peak to peak 1.5 v pp i&q output dc offset after dc cancellation 10 mv i&q output common mode 1.2 v
product # : uw2453 confidential doc. #: ds-2453-01 page 12/ 24 note 1: the rx vga step resolution is 1 db when the gain is set by the 3-wire bus. note 2: the voltage gain is measured by the voltage ratio between the differential output voltage at i or q output and the input voltage at the balun matching network input. note 3: guaranteed by design and characterization. note 4: at balun input two tones at 19 and 31 mhz offset from carrier frequency and each tone power ?35 dbm are applied. im3 is measured at 7 mhz. the inband gain at each setting is used to refer output im3 back to input. note 5: at balun input two tones at 19 and 26 mhz offset from carrier frequency and each tone power ?35 dbm are applied. im2 is measured at 7 mhz. the inband gain at each setting is used to refer output im2 back to input.
product # : uw2453 confidential doc. #: ds-2453-01 page 13/ 24 8 transmitter ac characterictics table 6. transmitter ac characteristics typical values are at t a = 25 o c, vdd = 2.85 v, lo frequency=2.447 ghz parameter condition min typ max unit rf carrier frequency 2.4 2.5 ghz lo frequency vco frequency divided by 2 2.4 2.5 ghz ofdm 17 dbm maximum rf output, single ended cck 20 dbm ofdm 2 dbm minimum rf output cck 5 dbm input resistance differential 20 k input capacitance differential 5 pf ofdm input level 100 200 mvrms cck input level 150 400 mvrms input common mode voltage 1.2 1.5 v tx maximum gain (uw2453) gs1 gs2 gs3 gs4 gs5 gs6 = 111111 (note 1) 38 dbm/ dbv tx maximum gain (UW2453L) gs1 gs2 gs3 gs4 gs5 gs6 = 111111 (note 1) 34 dbm/ dbv tx minimum gain (uw2453) gs1 gs2 gs3 gs4 gs5 gs6 = 000000 (note 1) 22.5 dbm/ dbv tx minimum gain (UW2453L) gs1 gs2 gs3 gs4 gs5 gs6 = 000000 (note 1) 18.5 dbm/ dbv gs1 8 gs2 4 gs3 2 gs4 1 tx vga gain step gs5 0.5 db carrier suppression at 100 mv rms input -20 dbc 11 <= offset frequency < 22 mhz -36 tx spectrum mask for cck at max power offset frequency >= 22 mhz -56 dbr offset frequency > = 10 mhz -26 offset frequency >= 20 mhz -36 tx spectrum mask for ofdm at max power offset frequency >=30 mhz -49 dbr
product # : uw2453 confidential doc. #: ds-2453-01 page 14/ 24 tx evm at 54 mbps and max power -28 -26 db sideband suppression without mismatch calibration 33 dbc rx to tx switching time with 1 db of final signal power level 2 us passband ripple (peak-to-peak 0~8.5 mhz ) 0.5 db max group delay (peak-to-peak 0~8.5 mhz ) 50 ns attenuation @30 mhz 50 db tx reconstruction filter attenuation @40 mhz 60 db tx noise floor at 40 mhz offset frequency. 1 mhz measurement bandwidth -110 dbm/hz 2 nd harmonic power single tone input at max power -15 dbm table 7. vco and pll ac characteristics typical values are at t a = 25 o c, vdd = 2.85 v, lo frequency=2.447 ghz parameter condition min typ max unit reference frequency 20/40 mhz reference clock level 600 mvpp reference clock input impedance 10 k pfd comparison frequency 20 mhz pll frequency resolution at 20 mhz comparison frequency 20 hz charge pump current programmable in 100, 200, 300 and 500 ua 100 500 ua charge pump current mismatch 10 % charge pump compliant voltage 0.3 vdd-0.3 v vco frequency 4.8 5.0 ghz lo frequency vco frequency divided by 2 2.4 2.5 ghz vco gain (kvco) 50 mhz/v at 100 khz offset -90 dbc/hz at 30 mhz offset -138 dbc/hz vco+pll phase noise after divide by 2 integrated from offset frequency 10 khz to 8.5 mhz -38 dbc
product # : uw2453 confidential doc. #: ds-2453-01 page 15/ 24 9 3-wire bus and register maps the uw2543 features an 80 mhz 3-wire bus for various control purposes. there are eight write-only registers defined and each register has 20 data bits. each register is identified by a four-digit address. the address is transmitted first before 20 bit data. the 3-wire bus consists of three digital lines: clock (pin clk), data (pin data) and enable (pin en). when pin en is asserted low and the clock is active, a0 is the first bit clocked into the uw2453 and d19 is the last bit. however, the 20 bit long data is latched by the rising edge of enable (en). note in this regular programming mode, the data length has to be 20 bits plus 4 address bits. hence, the reserved or test bits need to be programmed according to their default values. 9.1 3-wire bus data format address bits data bits a0 a1 a2 a3 d0 d1 d2 d3 d4 d5 ? d13 d14 d15 d16 d17 d18 d19 9.2 3-wire bus timing a3 a1 d0 a0 a1 a2 data en clk t f t r t w t p t sl d1 t sd t hd t de t ed d19 a0 figure 2. 3-wire bus timing diagram for regular programming table 8. 3-wire bus timing parameters parameters min typ max unit t r : clock rising time 2.5 ns t f : clock falling time 2.5 ns t p : clock period 12.5 ns t ed : 3-wire bus enable to disable setup time 2.5 ns t de : 3-wire bus disable to enable setup time 2.5 ns t sl : data latch setup time 2.5 ns t w : minimum 3-wire bus disable width 5 ns t sd : data setup time 2.5 ns t hd : data hold time 2.5 ns
product # : uw2453 confidential doc. #: ds-2453-01 page 16/ 24 9.3 register maps register address 0000 (a0a1a2a3): chip mode control bits name default description chip modes (see chip mode table) 0000: sleep 0001: idle 0010: rxtx_en 0011: cal_fil 0100: reserved 0101: cal_vco [19:16] mode 0000 0110: reserved 0111: reset [15] txgm 0 tx gain set mode 0: tx gain set by pins gs1~gs5 1: tx gain set by register bits txg [14] rxgm 0 rx gain set mode 0: rx gain set by pins gs1~gs7 1: rx gain set by register bits rxg s and rxg b [13] rssi off 1 rssi circuit powered up 0: rssi circuit powered up; 1: rssi circuit powered down [12:11] dcbta 00 2 nd dc blocking extra precharge time (note 1) 00: 0 ns; 01: 50 ns 10: 100 ns; 11: 150 ns [10:9] dcbtb 00 1 st and 2 nd dc blocking settling time (note 1) 00: 200 ns; 01: 250 ns 10: 300 ns; 11: 350 ns [8:7] dcbtc 00 2 nd dc blocking extra settling time (note 1) 00: 0 ns; 01: 50 ns 10: 100 ns; 11: 150 ns [6] dchp2 0 2 nd dc blocking highpass corner frequency [5] dchp 1 1 st dc blocking highpasss corner frequency [4:3] hpv 00 1 st dc blocking corner frequency controlling voltage (v) 00: 0; 01: 0.3; 10: 0.6; 11: 0.9 [2] lock/gs 1 pin is configured as 0: gs1~gs7 pin input enable control 1: lock detector output [1] rssirc 0 rssi range control 0: reduced range 1: normal range [0] 0 test/reserved bit note 1: the total dc cancellation time equals dcbta+dcbtb+dcbtc+50 ns.
product # : uw2453 confidential doc. #: ds-2453-01 page 17/ 24 table 9. chip mode description table chip mode description sleep sleep mode. whole chip powered down except 3-wire bus. 3-wire bus is always active for all chip modes when the ic power supply is on. idle idle mode. vco, synthesizer and reference clock buffer are powered up. the rest circuits are powered down. if pin rxtx=1, uw2453 is in the receive mode. lna, rx mixers, rx filters, rx vga, rx output buffers, vco, synthesizer, divide by 2, rx lo buffers and reference clock buffer are powered up. rssi is powered up or down independently by bit ?rssi off ?. the rest circuits are powered down. rxtx_en if pin rxtx=0, uw2453 is in the transmit mode. pa driver, tx mixers, tx vga, tx filters, vco, synthesizer, divide by 2, tx lo buffers and reference clock buffer are powered up. the rest circuits are powered down. cal_fil rx and tx filter calibration mode. only the filter tuning circuit and reference clock buffer are powered up. after the filter calibration, uw2453 enters the sleep mode automatically. cal_vco vco calibration mode. only vco, synthesizer, divide by 2, reference clock buffer and vco calibration circuit are powered up. after the vco calibration, uw2453 enters the idle mode automatically. reset reset mode. reset all register bits to default. enter sleep mode after reset. register address 0001: ? synthesizer bits name default description [19:14] n off 111010 offset integer dividing ratio. n off = n-64 (note 1) [13:12] cpc 11 charge pump current. 00: 100 ua; 01: 200 ua. 10: 300 ua; 11: 500 ua [11] div2 0 pll comparison frequency is half of reference frequency 0: yes; 1: no [10] lock en 0 pll lock indicator enable 0: enabled; 1: disabled [9] t widen 1 widen backlash time 0: no; 1: yes [8:0] 000000000 test/reserved bits note 1: denote channel center frequency f c in mhz, let 2f c /f ref = n+ n if div2=0 and f c /f ref = n+ n if div2=1. n is an integer and n is a fraction number.
product # : uw2453 confidential doc. #: ds-2453-01 page 18/ 24 register address 0010: ? synthesizer fractional divide ratio bits name default description [19:8] k 010110011001 integer input of ? modulator. (note 1) [7:0] test/reserved bits note 1: denote channel center frequency f c in mhz, let 2f c /f ref = n+ n if div2=0 and f c /f ref = n+ n if div2=1. n is an integer divide ratio and n is a fractional divide ratio. k equals to the integer part of n*2 12 . register address 0011: vco bits name default description [19] mvco 0 manual vco band selection enable 0: disabled; 1: enabled [18:14] vco band 10000 vco band selection if mvco=1 00000: highest band (frequency); 11111: lowest band [13:11] vco off 000 vco band offset from the calibrated band 000: no offset 001: offset one band higher 010: offset two bands higher 011: offset three bands higher 100: no offset 101: offset one band lower 110: offset two bands lower 111: offset three bands lower [10:9] vco_c 00 vco current level (ma) 00: normal; 01: normal+3 10: reserved; 11: normal+6 [8:7] rxlo_c 01 rx lo current level (ua) 00: 225; 01: 300; 10: 375; 11: 450 [6:4] txlo_c 000 tx lo current level (ua) 00: 200; 01: 250; 10: 300; 11: 350 [3:0] 00000 test/reserved bits register address 0100: receiver gain bits name default description [19:18] rxg s 11 rx stepped gain set by 3-wire bus when rxgm=1 00 or 01: 9 db; 10: 32 db; 11: 48 db. [17:13] rxg b 11111 rx vga gain set by 3-wire bus when rxgm=1 11111: 46 db; 11110: 44 db; ? 00001: -14 db; 00000: -16 db [12:0] 000000000000 test/reserved bits.
product # : uw2453 confidential doc. #: ds-2453-01 page 19/ 24 register address 0101: transmitter gain bits name default description [19:15] txg 11111 tx vga gain control 16 db range in 0.5db step set by 3-wire bus when txgm=1 11111:15.5 db; 11110: 15 db; 11101: 14.5 db; ?; 00001: 0.5 db; 00000: 0 db [14:12] ptat 010 tx power current parameter [11:8] pa1 1011 pa 1 st stage current setting [7:4] pa2 1010 pa 2 nd stage current setting [3:0] 0000 test/reserved bits register address 0110: filter bits name default description [19] rtxf en 0 manual rx/tx filter tuning enable 0: disabled; 1: enabled [18:11] rtxf tune 01101011 manual rx/tx filter tuning parameter 00000000: widest tx filter bandwidth ? 11111111: narrowest tx filter bandwidth [10:5] rxf off 000000 offset filter tuning value from the filter calibration for rx filter 000000: no offset 000001: minimum positive (increase filter bw) offset ? 011111: maximum positive offset 100000: no offset; 100001: minimum negative (decrease filter bw) offset ? 111111: maximum negative offset [4:0] txf off 00000 offset filter tuning value from the filter calibration for tx filter 00000: no offset 00001: minimum positive (increase filter bw) offset ? 11111: maximum positive offset
product # : uw2453 confidential doc. #: ds-2453-01 page 20/ 24 register address 0111: test bits name default description [19] txg ten 0 tx gain control enable in the test mode 0: disabled; 1: enabled [18:15] tst_pa 1111 pa driver current mode [14:7] tst_vga 11111000 tx vga current mode [6] tst_pa2 1 pa driver current reduced by half [5] tst_mix 1 mixer current mode [4:0] 00000 reserved
product # : uw2453 confidential doc. #: ds-2453-01 page 21/ 24 10 application notes 10.1 suggested power up sequence after the uw2453/UW2453L is powered up, certain procedure is required as follows (1) perform the filter calibration by programming register bits mode=0011. the calibration time is 10 us. after the calibration, uw2453 enters the sleep mode (mode=0000). (2) perform vco calibration with the channel planned to use by programming register bits mode=0101. reprogram the synthesizer if the default is not channel 8. the vco calibration takes 40 us. always perform vco calibration if there is a channel change afterwards. after the calibration, uw2453 enters the idle mode. it takes the pll less than 50 us to lock to the reference clock. 10.2 suggested rx stepped gain switching point the following switching points are valid for both agc with or without the on chip rssi assistance with two step switching. (1) gs1 gs2 switches from 11 to 10: input equals to -49 dbm at lna input; (2) gs1 gs2 switches from 10 to 01 or 00: input equals to -34 dbm at lna input; with one step switching, i.e., when gs1 gs2 is switched from 11 to 01 or 00, the switching point is -34 dbm. 10.3 suggested rx agc scheme using rssi output to perform the on chip rssi measurement, gs3 through gs7 have to be set to 1. for each of four gs1 and gs2 combinations, there is a rssi curve associated. the rssi curves with gs1gs2=11 and gs1gs2=01 or 00 cover the widest dynamic range and therefore, these two curves are suggested for rx agc with rssi assistance. the procedure is as follows: (1) turn on rx and set gs1~gs7=1111111 or other proper value; (2) wait 300 ns or more; (3) measure and average rssi for 300 ns, if the averaged rssi voltage is greater than 2.1 v, go step 4. otherwise, go step 9; (4) set gs1gs2=01 and keep gs3~gs7=11111; (5) wait 300 ns or more; (6) measure and average rssi for 300 ns; (7) use rssi curve for gs1gs2=11 to lookup the input power at lna; (8) use the above gain switching point to find the gs1~gs7 setting according to the lna input power and go step11; (9) use rssi curve for gs1gs2=01 to lookup the input power at lna; (10) use the above gain switching point to find the gs1~gs7 setting according to the lna input power and go step11; (11) set the rx gain obtained from step 8 or 10;
product # : uw2453 confidential doc. #: ds-2453-01 page 22/ 24 (12) use i&q adc do a fine digital rssi estimate and calculate the final gain adjustment in vga; (13) setting the final vga gain. note that the last fine gain adjustment only in vga. this means that the gs1 and gs2 switching points may not comply the suggested switching points. it is obvious that agc only needs a maximum of 3 times gain change to settle the correct rx gain. 10.4 suggested antenna diversity scheme using rssi output (1) turn on rx and set gs1~gs7=1111111; (2) energy is detected; (3) measure and average rssi output from the 1st antenna, if rssi voltage is greater than 1.8 v, no antenna diversity is needed and go step 9; (4) switch to the second antenna; (5) set gs1 or gs2 to 0 and set it back to 1 again after 25 ns (this activates the dc cancellation loop); (6) wait 300 ns or more; (7) measure and average rssi output from the 2nd antenna; (8) if rssi (1st) is greater than rssi (2nd) for at least 3 db, switch back to the 1st antenna and go to step 9. otherwise, just go to step 9; (9) do agc gain setting as shown in 10.3. note that the antenna diversity based on carrier sensing or carrier sensing plus rssi can follow a similar approach as described above.
product # : uw2453 confidential doc. #: ds-2453-01 page 23/ 24 11 package drawing
product # : uw2453 confidential doc. #: ds-2453-01 page 24/ 24
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